Methods of Programming Data in a Non-Volatile Memory Device and Methods of Operating a Nand Flash Memory Device Using the Same

ABSTRACT

Methods of programming data in a non-volatile memory cell are provided. A memory cell according to some embodiments may include a gate structure that includes a tunnel oxide layer pattern, a floating gate, a dielectric layer and a control gate sequentially stacked on a substrate, impurity regions that are formed in the substrate at both sides of the gate structure, and a conductive layer pattern that is arranged spaced apart from and facing the floating gate. Embodiments of such methods may include applying a programming voltage to the control gate, grounding the impurity regions and applying a fringe voltage to the conductive layer pattern to generate a fringe field in the floating gate.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 USC §119 to Korean PatentApplication No. 2007-59275 filed on Jun. 18, 2007, the contents of whichare herein incorporated by reference in its entirety.

FIELD OF THE INVENTION

The present invention relates to semiconductors in general and, moreparticularly, to methods of programming and operating memory devices.

BACKGROUND

Generally, semiconductor memory devices may be classified into avolatile memory devices and non-volatile memory devices. Volatile memorydevices may include, for example, dynamic random access memory (DRAM)devices and static random access memory (SRAM) device, among others andmay lose data over time. Non-volatile memory devices may continuouslystore data for significant periods of time. Non-volatile memory devicesmay include an electrically erasable programmable read only memory(EEPROM), a flash memory device, among others, and may be capable ofelectrically inputting/outputting data. Flash memory devices may includeprogressive types of EEPROM that may be capable of rapidly erasing data.Flash memory devices may electrically control input/output of data usingFowler-Nordheim (F-N) tunneling or hot electrons.

Flash memory devices may be classified into NAND type flash memorydevices and NOR type flash memory devices. The NOR type flash memorydevices may provide for rapid operation. In contrast, the NAND typeflash memory devices may be more readily integrated.

The NAND flash memory devices may use rapid programming and erasing at arelatively low voltage. To achieve the rapid programming and erasing ata relatively low voltage, it may be beneficial to provide each of unitcells in the NAND type flash memory device with a high coupling ratio.

In order to increase the coupling ratio, a high capacitance may beprovided between a floating gate pattern and a control gate pattern inthe cell. In contrast, a low capacitance may be provided between thefloating gate pattern and a semiconductor substrate.

The high capacitance between the floating gate pattern and the controlgate pattern may be provided by using a metal oxide having a highdielectric constant for a dielectric layer. When the dielectric layerincludes the metal oxide having the high dielectric constant, asufficient capacitance may be provided without increasing of aneffective surface area of the floating gate pattern. In this regard, thefloating gate pattern may be thin by forming the dielectric layer onlyon an upper surface of the floating gate pattern and not on a sidewallof the floating gate pattern.

Further, when the floating gate pattern is thin, interference betweenthe adjacent floating gate patterns may be reduced. Therefore,distribution of threshold voltages between the cells caused by theinterference may also be decreased.

However, when the dielectric layer is formed using the material having ahigh dielectric constant, charges in the floating gate pattern may bepartially discharged due to the dielectric layer. Particularly, aplurality of trap sites may exist in the dielectric layer having thehigh dielectric constant. Accordingly, the charges in the floating gatepattern may escape through the trap in the dielectric layer via anelectric field between the floating gate pattern and the control gatepattern and thus the charges in the floating gate pattern may bepartially lost. The partial loss of the charges in the floating gatepattern may result in changes and/or loss of the data and malfunctionsof the NAND type flash memory devices. As a result, the NAND type memorydevices may have low reliability.

Therefore, a non-volatile memory device that is formed using thematerial having a high dielectric constant and that provides stablefunctionality and good reliability may be desired. Further, methods ofoperating the non-volatile memory device that may avoid the malfunctionsand improve the reliability, may also be desired.

SUMMARY OF THE INVENTION

Some embodiments of the present invention include methods of programmingdata in a memory cell that includes a gate structure having a tunneloxide layer pattern, a floating gate, a dielectric layer and a controlgate sequentially stacked on a substrate. In some embodiments, the gatestructure may include impurity regions that are formed in the substrateat both sides of the gate structure and a conductive layer pattern thatis arranged spaced apart from and facing the floating gate. Someembodiments of such methods include applying a programming voltage tothe control gate, grounding the impurity regions and applying a fringevoltage to the conductive layer pattern to generate a fringe field inthe floating gate.

In some embodiments, applying a fringe voltage includes applying thefringe voltage to the conductive layer pattern through a gate of a dummytransistor that is adjacent the memory cell and electrically connectedto the conductive layer pattern. Some embodiments provide that thefringe voltage is less than the programming voltage. In someembodiments, the fringe voltage is about 30% to about 70% of theprogramming voltage.

Some embodiments provide that applying the fringe voltage includesapplying the fringe voltage spaced apart from sidewalls of the floatinggates facing each other along a widthwise direction of the memory cell.Some embodiments may include controlling the programming voltage and thefringe voltage to provide the floating gate with a potential forprogramming the data via the programming voltage and the fringe voltage.

Some embodiments of the present invention include methods of programmingdata in a NAND flash memory. Some embodiments of such methods mayinclude applying a programming voltage to a word line connected to aselected cell of multiple cells in the NAND flash memory device,applying a pass voltage to other word lines connected to ones of thecells that are in a cell string that includes the selected cell,grounding a bit line connected to the selected cell, and applying afringe voltage to a portion of the selected cell that is spaced apartfrom sidewalls of floating gates in the selected cell to generate afringe field in the floating gates, the fringe voltage being lower thanthe programming voltage.

In some embodiments, each of the cells including the selected cell in acell block includes a gate structure and a conductive layer and the gatestructure includes a tunnel oxide layer pattern, a floating gate, adielectric layer and a control gate sequentially stacked on a substrate.Some embodiments provide that the conductive layer pattern that isarranged spaced apart from and facing the floating gate and applying thefringe voltage includes applying the fringe voltage through theconductive layer pattern.

In some embodiments, the conductive layer pattern is connected to a gateelectrode of a dummy transistor and applying the fringe voltage includesapplying the fringe voltage through the gate electrode of the dummytransistor. Some embodiments provide that the fringe voltage is greaterthan a threshold voltage of the dummy transistor.

In some embodiments, applying the fringe voltage includes applying thefringe voltage between the floating gates in a cell block that includesthe selected cell while the selected cell is programmed. In someembodiments, applying the fringe voltage includes applying the fringevoltage between sidewalls of the floating gates facing each other alonga widthwise direction of the memory cell. Some embodiments provide thatthe fringe voltage is substantially the same as the pass voltage. Someembodiments provide that the fringe voltage is about 30% to about 70% ofthe programming voltage. In some embodiments, the pass voltage is lessthan the programming voltage and each of cells is turned-on by the passvoltage.

Some embodiments include applying a power voltage to other bit linesarranged at both sides of the bit line that is connected to the selectedcell. Some embodiments include controlling the programming voltage andthe fringe voltage to provide the floating gate with a potential forprogramming the data via the programming voltage and the fringe voltage.

Some embodiments of the present invention include methods of erasingdata from a NAND flash memory device. Some embodiments of such methodsmay include grounding word lines and bit lines of the NAND flash memorydevice, applying an erasing voltage to a channel region of multiplecells in the NAND flash memory device, and grounding a portion of aconductive layer spaced apart from sidewalls of floating gates in thecells. In some embodiments, the floating gates face each other along awidthwise direction of the memory device.

Some embodiments of the present invention include methods of readingdata in a NAND flash memory device. Some embodiments of such methods mayinclude grounding a word line connected to a selected cell of multiplecells in the NAND flash memory device and applying a pass voltage toother word lines that are connected to ones of the cells in a cellstring that includes the selected cell. Methods may include applying areading voltage to a bit line that is connected to the selected cell andapplying a fringe voltage or a ground voltage to a conductive portionthat is spaced apart from sidewalls of floating gates in the selectedcell.

In some embodiments, applying the fringe voltage or the ground voltageincludes applying the fringe voltage or ground voltage to conductiveportions spaced apart from sidewalls of the floating gates facing eachother along a widthwise direction of a channel in the cells of a cellblock that includes the selected cell. In some embodiments, the fringevoltage or the ground voltage is applied across sidewalls of thefloating gates facing each other along a widthwise direction of achannel in the cells of a cell block that includes the selected cell.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view illustrating a unit cell of a transistor for whichprogramming methods in accordance with some embodiments of the presentinvention is applicable.

FIG. 2 is a perspective view illustrating a cell array for whichoperating methods of NAND flash memory devices in accordance with someembodiments of the present invention is applicable.

FIG. 3 is a cross-sectional view taken along a line I-I′ in FIG. 2.

FIG. 4 is a cross-sectional view taken along a line II-II′ in FIG. 2.

FIG. 5 is a cross-sectional view taken along a line III-III′ in FIG. 2.

FIG. 6 is a circuit diagram illustrating the cell array of the NANDflash memory device in FIG. 2.

FIG. 7 is a graph showing pass voltage ranges used as data is programmedin a selection cell of the cell array in FIG. 6.

DESCRIPTION OF THE EMBODIMENTS

The present invention is described more fully hereinafter with referenceto the accompanying drawings, in which example embodiments of thepresent invention are illustrated. The present invention may, however,be embodied in many different forms and should not be construed aslimited to the example embodiments set forth herein. Rather, theseembodiments are provided so that this disclosure will be thorough andcomplete, and will fully convey the scope of the present invention tothose skilled in the art. In the drawings, the sizes and relative sizesof layers and regions may be exaggerated for clarity.

It will be understood that when an element or layer is referred to asbeing “on,” “connected to” or “coupled to” another element or layer, itcan be directly on, connected or coupled to the other element or layeror intervening elements or layers may be present. In contrast, when anelement is referred to as being “directly on,” “directly connected to”or “directly coupled to” another element or layer, there are nointervening elements or layers present. Like reference numerals refer tolike elements throughout. As used herein, the term “and/or” includes anyand all in a mixture of one or more of the associated listed items.

It will be understood that, although the terms first, second, third etc.may be used herein to describe various elements, components, regions,layers and/or sections, these elements, components, regions, layersand/or sections should not be limited by these terms. These terms areonly used to distinguish one element, component, region, layer orsection from another region, layer or section. Thus, a first element,component, region, layer or section discussed below could be termed asecond element, component, region, layer or section without departingfrom the teachings of the present invention.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,”“upper” and the like, may be used herein for ease of description todescribe one element or feature's relationship to another element(s) orfeature(s) as illustrated in the figures. It will be understood that thespatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. For example, if the device in thefigures is turned over, elements described as “below” or “beneath” otherelements or features would then be oriented “above” the other elementsor features. Thus, the exemplary term “below” can encompass both anorientation of above and below. The device may be otherwise oriented(rotated 90 degrees or at other orientations) and the spatially relativedescriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the presentinvention. As used herein, the singular forms “a,” “an” and “the” areintended to include the plural forms as well, unless the context clearlyindicates otherwise. It will be further understood that the terms“comprises” and/or “comprising,” when used in this specification,specify the presence of stated features, integers, steps, operations,elements, and/or components, but do not preclude the presence oraddition of one or more other features, integers, steps, operations,elements, components, and/or groups thereof.

Example embodiments of the present invention are described herein withreference to cross-section illustrations that are schematicillustrations of idealized embodiments (and intermediate structures) ofthe present invention. As such, variations from the shapes of theillustrations as a result, for example, of manufacturing techniquesand/or tolerances, are to be expected. Thus, example embodiments of thepresent invention should not be construed as limited to the particularshapes of regions illustrated herein but are to include deviations inshapes that result, for example, from manufacturing. For example, animplanted region illustrated as a rectangle will, typically, haverounded or curved features and/or a gradient of implant concentration atits edges rather than a binary change from implanted to non-implantedregion. Likewise, a buried region formed by implantation may result insome implantation in the region between the buried region and thesurface-through which the implantation takes place. Thus, the regionsillustrated in the figures are schematic in nature and their shapes arenot intended to illustrate the actual shape of a region of a device andare not intended to limit the scope of the present invention.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which the present invention belongs. Itwill be further understood that terms, such as those defined in commonlyused dictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art andwill not be interpreted in an idealized or overly formal sense unlessexpressly so defined herein.

Hereinafter, methods of programming data in a unit cell transistor of aNAND flash memory device are provided. In this regard, structures of aunit cell transistor for which some embodiments of programming methoddescribed herein may be used are explained. Reference is now made toFIG. 1, which is a plan view illustrating the unit cell transistor forwhich programming methods in accordance with some embodiments of thepresent invention are applicable. The unit cell transistor may include agate structure formed on a semiconductor substrate (not shown). The gatestructure may include a tunnel oxide layer pattern (not shown), afloating gate 10, a dielectric layer pattern (not shown) and/or acontrol gate sequentially stacked on the semiconductor substrate.

Impurity regions 12 may be formed in the semiconductor substrateadjacent the sidewalls of the floating gate 10 in a first direction.Conductive layer patterns 14 may be formed on the semiconductorsubstrate adjacent the floating gate 10 in a second direction that maybe substantially perpendicular to the first direction. The conductivelayer patterns 14 maybe spaced apart from the floating gate 10. Further,the conductive layer patterns 14 may face the floating gate 10.

Hereinafter, methods of programming data in the unit cell transistor ofthe NAND flash memory device in accordance with embodiments illustratedin FIG. 1 may be provided in detail. Some embodiments provide that aprogramming voltage may be applied to the control gate. In someembodiments, the impurity regions 12 may then be grounded.

A fringe voltage may be applied to the conductive layer patterns 14 toform a fringe field in the floating gate 10. In some embodiments, thefringe voltage may be lower than the programming voltage. Someembodiments provide that the fringe voltage may be about 30% to about70% of the programming voltage. In some embodiments, the fringe voltagemay be about 50% of the programming voltage.

Some embodiments provide that when the fringe voltage is applied to theconductive layer patterns 14, the fringe field may be formed between thefloating gate 10 and the conductive layer patterns 14. As a result, apotential of the floating gate 10 may increase.

That is, the potential of the floating gate 10 may be increased by thefringe voltage and/or the programming voltage that is applied to thecontrol gate. In this regard, some embodiments provide that the levelsof the programming voltage and the fringe voltage may be adjusted toprovide the floating gate 10 with the potential capable of performingthe programming operation.

When the programming voltage and the fringe voltage are applied suchthat the potential of the floating gate 10 increases and the impurityregions 12 are grounded, charges may be stored in the floating gate 10through the tunnel oxide layer by F-N tunneling.

In this regard, some embodiments provide that when the potential of thefloating gate 10 is increased via the fringe voltage, the programmingvoltage may be slightly decreased as compared to that of a programmingoperation in the absence of the fringe voltage. Accordingly, theprogramming operation may be performed with a lower programming voltagethan may be provided in a conventional programming voltage applied tothe control gate. In some embodiments, when the programming voltageapplied to the control gate becomes lower, the charges may not betrapped in the dielectric layer pattern, because the electric fieldbetween the control gate and the floating gate 10 may be decreased. Inthis regard, the cell transistor may have improved reliability.

In some embodiments, a programming voltage that is substantially thesame as the conventional programming voltage may be applied to thecontrol gate in conjunction with the application of the fringe voltage.Some embodiments provide that the potential of the floating gate 10 mayincrease compared to that of a conventional floating gate due to thefringe voltage, which may increase a programming speed.

As described above, the programming voltage applied to the control gatemay vary by adjusting the fringe voltage. In some embodiments, the celltransistor may have improved operational characteristics and reliabilityby changing the programming voltage.

Hereinafter, methods of erasing data from the unit cell transistor andreading the data in the unit cell transistor are illustrated in detailwith reference to FIG. 1. In some embodiments, to erase the data fromthe unit cell transistor, the control gate and the impurity regions 12may be grounded. Some embodiments provide that an erasing voltage may beapplied to a channel region of the unit cell transistor. In someembodiments, the conductive layer patterns 14 may be grounded to preventthe fringe voltage from being generated in the floating gate 10.

In some embodiments, the control gate is grounded to read the data inthe unit cell transistor. A reading voltage may be applied to any one ofthe impurity regions 12. Some embodiments provide that the fringevoltage or a ground voltage may be applied to the conductive layerpatterns 14. In some embodiments, when the fringe voltage is applied tothe conductive layer patterns 14, a current may be increased due to alow threshold voltage of the cell transistor. In contrast, when theconductive layer patterns 14 are grounded, reading characteristics maybe substantially the same as conventional reading characteristics,because the fringe voltage is not generated.

Reference is now made to FIG. 2, which is a perspective viewillustrating a cell array which may use an operating method of a NANDflash memory device in accordance with some embodiments of the presentinvention. Reference is also made to FIG. 3, which is a cross-sectionalview taken along a line I-I′ in FIG. 2, FIG. 4, which is across-sectional view taken along a line II-II′ in FIG. 2, and FIG. 5,which is a cross-sectional view taken along a line III-III′ in FIG. 2.

In some embodiments, a semiconductor substrate 100 has isolation regionsand active regions. Some embodiments provide that isolation trenches maybe formed in the isolation regions of the semiconductor substrate 100.In some embodiments, isolation layer patterns 102 are formed in theisolation trenches. In some embodiments, the isolation layer patterns102 may have a linear shape extending along a first direction. Someembodiments provide that the isolation layer patterns 102 may bearranged in parallel with each other.

In some embodiments, the active regions correspond to portions of thesemiconductor substrate 100 exposed by the isolation layer patterns 102.The active regions may have a linear shape extending along the firstdirection. Some embodiments provide that the active regions may bearranged in parallel with one another.

In some embodiments, a cell gate structure 114 is formed on thesemiconductor substrate 100 of each of the active regions. Someembodiments provide that the cell gate structure 114 includes a tunneloxide layer pattern 106, a floating gate 108, a dielectric layer pattern110 and/or a control gate 112 that may be sequentially stacked on thesemiconductor substrate 100. In some embodiments, the tunnel oxide layerpattern 106 is formed on the semiconductor substrate 100 of the activeregion. Some embodiments provide that the floating gates 108 may includean isolated island shape and may be formed on the tunnel oxide layerpattern 106 to define isolated unit active regions. The floating gates108 may be formed in the unit active region defined by the isolationlayer patterns 102. Some embodiments provide that the floating gates 108may correspond to elements of each of the unit cells connected to eachother in series. In some embodiments, the dielectric layer pattern 110is formed on the floating gate 108. The dielectric layer pattern 110 mayinclude a linear shape extending along a second direction that may besubstantially perpendicular to the first direction. Some embodimentsprovide that the dielectric layer pattern 110 may include metal oxidethat may have a high dielectric constant. In some embodiments, thecontrol gate 112 is formed on the dielectric layer pattern 110. Thecontrol gate 112 may have a linear shape extending along the seconddirection. Some embodiments provide that the linear control gate 112 maybe used as a word line.

In some embodiments, impurity regions 128 may be formed in thesemiconductor substrate 100 of the active region at both sides of thefloating gate 108.

Some embodiments provide that conductive layer patterns 116 are formedbetween the floating gates 108. In some embodiments, the conductivelayer patterns 116 may be spaced apart from the floating gates 108. Someembodiments provide that the conductive layer patterns 116 may have alinear shape extending along the first direction. In some embodiments,the conductive layer patterns 116 may be positioned on the isolationlayer patterns 102 between the floating gates 108. Some embodimentsprovide that the conductive layer patterns 116 may have upper surfacesthat make contact with a lower surface of the dielectric layer pattern110. In this regard, the conductive layer patterns 116 may not beelectrically connected to the control gate 112.

In some embodiments, the cell gate structures 114 maybe connected toeach other in series to form a single string. Some embodiments providethat a dummy gate structure 124 is formed at one end of the cell gatestructures 114 that are connected to each other in series. The dummygate structure 124 may include a gate oxide layer 118, a first gateelectrode 120 and/or an upper conductive line 114, that may besequentially stacked. In contrast with the cell gate structures 114, thedielectric layer pattern 110 may not be interposed between the firstgate electrode 120 and the upper conductive line 122. In someembodiments, the upper conductive line 122 is electrically connectedbetween the first gate electrodes 120 arranged in parallel with eachother along the second direction. Some embodiments provide that theupper conductive line 122 may have a linear shape extending along thesecond direction and making contact with an upper surface of the firstgate electrode 120.

In some embodiments, impurity regions (not shown) are formed at bothsides of the dummy gate structures 124 to form a dummy transistor. Someembodiments may include one or more than one dummy gate structures 124.Some embodiment provide that the dummy transistor may be seriallyconnected to the cell string.

In some embodiments, a ground selection line (GSL) 130 is connected toone end of the dummy gate structure 124 at one end of the cell string.Some embodiments provide that a string selection line (SSL) 120 isconnected to the other end of the cell string. In some embodiments,although not depicted in drawings, the string selection line 120 may beconnected to one end of the dummy gate structure 124 at one end of thecell string and the ground selection line 130 may be connected to theother end of the cell string. Some embodiments provide that impurityregions may be formed at both sides of the string selection line and theground selection line.

As shown in FIG. 5, the dummy gate structure 124 may be electricallyconnected to the conductive layer patterns 116. Some embodiments providethat the upper conductive line 122 in the dummy gate structure 124 has alinear shape extending along the second direction. In some embodiments,the conductive layer patterns 116 have a linear shape extending alongthe first direction. Thus, some embodiments provide that upper surfacesof the conductive layer patterns 116 and a lower surface of the upperconductive line 122 make contact with each other at an intersectionpoint between the upper conductive line 122 and the conductive layerpatterns 116. As a result, the dummy gate structure 124 and theconductive layer patterns 116 may be electrically connected to eachother.

In some embodiments, although not depicted in drawings, a common sourceline (CSL) may be connected to the impurity regions of the groundselection line in each of the cell strings.

Reference is now made to FIG. 6, which is a circuit diagram illustratingthe cell array of the NAND flash memory device in FIG. 2 that shows asingle cell block commonly owning the word lines. Some embodimentsprovide that the cell block includes m numbers of bit lines.

Hereinafter, methods of programming data in a selected cell inaccordance with some embodiments of FIG. 6 is provided. In someembodiments, the data is programmed in the selected cell at anintersection of the bit line BL1 and the word line WL30 in FIG. 6.

Some embodiments provide that a programming voltage Vpgm is applied tothe selection word line WL30 connected to a selected cell 200. In someembodiments, the programming voltage Vpgm may be lower than aprogramming voltage used for a NAND flash memory device without theconductive layer patterns between the floating gates. When theprogramming voltage Vpgm is low, an electric field between the selectionword-line WL30 and the floating gate of the selected cell 200 may bedecreased. Accordingly, charges may not be trapped in the dielectriclayer pattern between the selection word line WL30 and the floating gateso that loss of the charges may be suppressed. When the loss of thecharges in the floating gate is suppressed, the NAND flash memory devicemay have improved operational characteristics and reliability.

In some embodiments, the programming voltage Vpgm may be substantiallythe same as the programming voltage used for the NAND flash memorydevice without the conductive layer pattern. In such embodiments, aprogramming speed may increase.

Some embodiments provide that a pass voltage Vpass is applied to therest word lines WL0 to WL29 and WL31 except for the selection word lineWL30. In such embodiments, the data may not be not programmed in thecells of the cell array by the pass voltage Vpass. In this regard, thepass voltage Vpass may be lower than the programming voltage Vpgm. Insome embodiments, the pass voltage Vpass may be about 30% to about 70%of the programming voltage Vpgm. Some embodiments provide that, sincethe programming voltage Vpgm may be lower than the conventionalprogramming voltage, the pass voltage Vpass may be lower than aconventional pass voltage.

Some embodiments provide that the pass voltage Vpass may be no less thana threshold voltage of each of cells regardless of the data in thecells. If the pass voltage Vpass is applied to the rest word lines WL0to WL29 and WL31 except for the selection word line WL30, rest cells inthe cell block except for the selected cell may be turned-on.

In some embodiments, the bit line BL1 connected to the selected cell 200is grounded. In such embodiments, a high voltage difference may begenerated between the selection word line WL30 and a channel region inthe selected cell 200. Accordingly, the charges in the channel regionmay be tunneled by the voltage difference to program the data in thefloating gate.

Some embodiments provide that a power voltage Vcc is applied to the bitlines BL0 and BL2 to BLm-1 including the word lines together with thecells of the selection string. If the power voltage Vcc is applied tothe bit lines BL0 and BL2 to BLm-1 connected to adjacent strings, a highvoltage substantially the same as the power voltage Vcc may be appliedto channel regions of the cells in the adjacent strings. In this regard,since the high voltage may be applied to the channel regions of thecells in the adjacent string, a voltage difference for programming thedata may not be generated between the selection word line WL30 and thechannel region in a program inhibition cell 204 included in theword-line WL30. Some embodiments provide that the pass voltage Vpass maybe applied to other cells not including the word line WL30 and thus theprogramming operation may not be performed.

In some embodiments, a fringe voltage Vfringe is applied to theconductive layer pattern 116 to form a fringe field in the floating gateof the selected cell 200. Some embodiments provide that the fringevoltage may be applied between sidewalls of floating gates facing eachother in a widthwise direction of channels of the cells.

In some embodiments, the fringe voltage Vfringe may be lower than theprogramming voltage. Some embodiments provide that the fringe voltageVfringe may be about 30% to about 70% of the programming voltage Vpgm.Some embodiments provide that the fringe voltage Vfringe may be about50% of the programming voltage Vpgm. In some embodiments, the fringevoltage Vfringe may be substantially the same as the pass voltage Vpass

In some embodiments, the conductive layer patterns 116 and the gateelectrode of the dummy transistor DM may be electrically connected toeach other. Some embodiments provide that the fringe voltage Vfringe maybe applied through the gate electrode of the dummy transistor DM. Insome embodiments, since it the dummy transistor DM may be maintained ina turned-on state during the programming operation, the fringe voltageVfringe may be higher than a threshold voltage of the dummy transistorDM. Some embodiments provide that the fringe voltage Vfringe may besubstantially the same as the pass voltage Vpass.

As shown in FIGS. 2 to 5, the first gate electrode 120 of the dummytransistor may be connected to the entire conductive layer patterns 116of the cell block through the upper conductive line 122. In this regard,some embodiments provide that the fringe voltage Vfringe may be appliedto the entire floating gates of the cell block through the upperconductive line 122.

In some embodiments, the potential of the floating gate may be increasedby the programming voltage and the fringe voltage. That is, theprogramming voltage and the fringe voltage may be controlled to providethe floating gate with the potential for performing the programmingoperation.

Some embodiments provide that when performing the programming operation,the power voltage Vcc may be applied to the string selection line SSLand the ground selection line GSL may be grounded. In some embodiments,the power voltage Vcc is applied to the common source line CSL. When thevoltages are thus applied, the charges may be stored in the floatinggate of the selected cell to program the selected cell. In someembodiments, the fringe voltage may be applied to a portion adjacent thefloating gate of the selected cell so that the potential of the floatinggate may be increased. In this manner, the programming voltage may bereduced as compared to a programming operation that is performed withoutapplication of the fringe voltage.

Referring back to FIG. 6, while programming the selected cell, it may bedesirable to prevent other cells 204 (hereinafter, referred to as firstprogram inhibition cells) including the word line WL30 and the selectedcell 200 from being programmed. Regarding the first program inhibitioncell 204 in a string of the bit line BLm-1, while the selected cell 200is programmed, the pass voltage Vpass may be applied to the word linesof other cells that are serially connected to the first programinhibition cell 204.

In some embodiments, when the pass voltage Vpass is less than thethreshold voltage of the cells, the cells may not be sufficientlyturned-on and the power voltage Vcc may not be applied to the channelregion through the bit line BLm-1. In this regard, some embodimentsprovide that the channel region of the first program inhibition cell 204may not be sufficiently increased and thus the first program inhibitioncell 204 may be partially programmed.

However, the fringe voltage Vfringe may be applied to a portion spacedapart from the floating gates of the cell block while programming, sothat the threshold voltage for turning-on the word lines of the cells inthe cell block may be reduced. In this regard, although the pass voltageVpass may be less than a conventional pass voltage, the first programinhibition cell 204 may not be programmed while the selected cell isprogrammed. Accordingly, some embodiments provide that the pass voltageVpass may be substantially less than a conventional pass voltage. Insome embodiments, since the bit line BL1 connected to the second programinhibition cell 206 is grounded, the cells including the bit line andthe selected cell 200 may be programmed as the pass voltage Vpassincreases.

In some embodiments, the fringe voltage Vfringe may be applied to aportion spaced apart from the floating gates of the cell block duringprogramming. In this regard, the programming operation may beaccomplished at a relatively low voltage. Some embodiments provide thatthe pass voltage Vpass may be reduced to prevent the second programinhibition cell 206 from being programmed during the selected cell 200programming.

Accordingly, some embodiments provide that the pass voltage may begreater than the threshold voltage for turning-on the cells and lowerthan the programming voltage. A voltage window, which defines anallowable pass voltage range, may be wider than a difference between thethreshold voltage and the programming voltage. Some embodiments providethat as the voltage window increases, data errors caused by the passvoltage Vpass may be reduced. Accordingly, in some embodiments, althoughthe pass voltage Vpass may exceed an allowable range set by a user,programming failures may be reduced and/or avoided.

Reference is now made to FIG. 7, which is a graph showing pass voltageranges used while data is programmed in a selection cell of the cellarray in FIG. 6. An X-axis represents the pass voltage and a Y-axisindicates threshold voltages of the first program inhibition cell andthe second program inhibition cell.

A curved line 50 represents transition of the threshold voltage by thepass voltages in the first program inhibition cell while the selectedcell is programmed using the method in accordance with some embodimentsof the present invention. In contrast, a curved line 52 representstransition of the threshold voltage by the pass voltages in the firstprogram inhibition cell while the selected cell is programmed using aconvention method.

As illustrated, the curved line 50 is shifted along a left directioncompared to the curved line 52. Further, when the threshold formaintaining the former data is −1V, an allowable pass voltage Vpass1 inaccordance with methods described herein may be substantially less thanan allowable pass voltage of conventional methods.

A curved line 60 represents a change in the threshold voltage resultingfrom the pass voltages in the second program inhibition cell while theselected cell is programmed using method accordance with someembodiments of the present invention. A curved line 62 represents achange in the threshold voltage resulting from the pass voltages in thesecond program inhibition cell while the selected cell is programmedusing a conventional method

As is illustrated, the curved line 60 is shifted along a left directioncompared to the curved line 62. Further, if the threshold formaintaining the former data is about −1V, an allowable pass voltageVpass2 in accordance with some embodiments of the methods describedherein may be substantially less than an allowable pass voltage of theconventional method.

In FIG. 7, Vpass window1 represents a pass voltage window whileprogramming using some embodiments of methods described herein. Vpasswindow2 represents a pass voltage window while programming using aconventional method. Although the pass voltage level of the presentmethod may be slightly lower than that of the conventional method, itcan be noted that the pass voltage windows of the present method may besubstantially the same as that of the conventional method. In thisregard, disturbance of the programming operation may not be increased asa result of the low pass voltage level relative to that of theconventional method.

According to some embodiments of the present invention, programmingefficiency of the non-volatile memory device may be increased so thatthe data may be programmed using a relatively low voltage. Further, thecharges may not be trapped in the dielectric layer while performing aprogramming operation. Accordingly, the non-volatile memory device mayhave improved operational characteristics and reliability.

While the present invention has been particularly shown and describedwith reference to exemplary embodiments thereof, it will be understoodby those of ordinary skill in the art that various changes in form anddetails may be made therein without departing from the spirit and scopeof the present invention as defined by the following claims.

1. A method of programming data in a memory cell, the memory cellincluding a gate structure that includes a tunnel oxide layer pattern, afloating gate, a dielectric layer and a control gate sequentiallystacked on a substrate, impurity regions that are formed in thesubstrate at both sides of the gate structure, and a conductive layerpattern that is arranged spaced apart from and facing the floating gate,the method comprising: applying a programming voltage to the controlgate; grounding the impurity regions; and applying a fringe voltage tothe conductive layer pattern to generate a fringe field in the floatinggate.
 2. The method of claim 1, wherein applying a fringe voltagecomprises applying the fringe voltage to the conductive layer patternthrough a gate of a dummy transistor that is adjacent the memory celland electrically connected to the conductive layer pattern.
 3. Themethod of claim 1, wherein the fringe voltage is less than theprogramming voltage.
 4. The method of claim 3, wherein the fringevoltage is about 30% to about 70% of the programming voltage.
 5. Themethod of claim 1, wherein applying the fringe voltage comprisesapplying the fringe voltage spaced apart from sidewalls of the floatinggates facing each other along a widthwise direction of the memory cell.6. The method of claim 1, further comprising controlling the programmingvoltage and the fringe voltage to provide the floating gate with apotential for programming the data via the programming voltage and thefringe voltage.
 7. A method of programming data in a NAND flash memory,the method comprising: applying a programming voltage to a word lineconnected to a selected cell of a plurality of cells in the NAND flashmemory device; applying a pass voltage to other word lines connected toones of the plurality of cells that are in a cell string that includesthe selected cell; grounding a bit line connected to the selected cell;and applying a fringe voltage to a portion of the selected cell that isspaced apart from sidewalls of floating gates in the selected cell togenerate a fringe field in the floating gates, the fringe voltage beinglower than the programming voltage.
 8. The method of claim 7, whereineach of the plurality of cells including the selected cell in a cellblock includes a gate structure and a conductive layer, wherein the gatestructure includes a tunnel oxide layer pattern, a floating gate, adielectric layer and a control gate sequentially stacked on a substrate,wherein the conductive layer pattern that is arranged spaced apart fromand facing the floating gate, and wherein applying the fringe voltagecomprises applying the fringe voltage through the conductive layerpattern.
 9. The method of claim 8, wherein the conductive layer patternis connected to a gate electrode of a dummy transistor, and whereinapplying the fringe voltage comprises applying the fringe voltagethrough the gate electrode of the dummy transistor.
 10. The method ofclaim 9, wherein the fringe voltage is greater than a threshold voltageof the dummy transistor.
 11. The method of claim 7, wherein applying thefringe voltage comprises applying the fringe voltage between thefloating gates in a cell block that includes the selected cell while theselected cell is programmed.
 12. The method of claim 7, wherein applyingthe fringe voltage comprises applying the fringe voltage betweensidewalls of the floating gates facing each other along a widthwisedirection of the memory cell.
 13. The method of claim 7, wherein thefringe voltage is substantially the same as the pass voltage.
 14. Themethod of claim 7, wherein the fringe voltage is about 30% to about 70%of the programming voltage.
 15. The method of claim 7, wherein the passvoltage is less than the programming voltage and wherein each of cellsis turned-on by the pass voltage.
 16. The method of claim 7, furthercomprising applying a power voltage to other bit lines arranged at bothsides of the bit line that is connected to the selected cell.
 17. Themethod of claim 7, further comprising controlling the programmingvoltage and the fringe voltage to provide the floating gate with apotential for programming the data via the programming voltage and thefringe voltage.
 18. A method of erasing data from a NAND flash memorydevice, the method comprising: grounding word lines and bit lines of theNAND flash memory device; applying an erasing voltage to a channelregion of a plurality of cells in the NAND flash memory device; andgrounding a portion of a conductive layer spaced apart from sidewalls offloating gates in the plurality of cells.
 19. The method of claim 18,wherein the floating gates face each other along a widthwise directionof the memory device.
 20. A method of reading data in a NAND flashmemory device, the method comprising: grounding a word line connected toa selected cell of a plurality of cells in the NAND flash memory device;applying a pass voltage to other word lines that are connected to onesof the plurality of cells in a cell string that includes the selectedcell; applying a reading voltage to a bit line that is connected to theselected cell; and applying a fringe voltage or a ground voltage to aconductive portion that is spaced apart from sidewalls of floating gatesin the selected cell.
 21. The method of claim 20, wherein applying thefringe voltage or the ground voltage comprises applying the fringevoltage or ground voltage to conductive portions spaced apart fromsidewalls of the floating gates facing each other along a widthwisedirection of a channel in the cells of a cell block that includes theselected cell.
 22. The method of claim 20, wherein the fringe voltage orthe ground voltage is applied across sidewalls of the floating gatesfacing each other along a widthwise direction of a channel in the cellsof a cell block that includes the selected cell.